From 9ffdd32550db34edb49e07d152dc9324fe7083a9 Mon Sep 17 00:00:00 2001 From: "kaf24@scramble.cl.cam.ac.uk" Date: Sat, 14 Aug 2004 15:37:12 +0000 Subject: [PATCH] bitkeeper revision 1.1159.31.1 (411e31a8whkN5pph5aGYDZEaAAg8eg) Update some Xen files to Linux 2.4.26. Hopefully will fix some IRQ routing problems that have been reported. --- .rootkeys | 3 - xen/arch/x86/acpi.c | 133 ++++++++---- xen/arch/x86/io_apic.c | 6 +- xen/arch/x86/pci-irq.c | 1 + xen/arch/x86/setup.c | 5 - xen/drivers/pci/setup-bus.c | 400 ------------------------------------ xen/drivers/pci/setup-irq.c | 71 ------- xen/drivers/pci/syscall.c | 144 ------------- xen/include/asm-x86/acpi.h | 66 +++--- xen/include/xen/pci_ids.h | 27 ++- 10 files changed, 156 insertions(+), 700 deletions(-) delete mode 100644 xen/drivers/pci/setup-bus.c delete mode 100644 xen/drivers/pci/setup-irq.c delete mode 100644 xen/drivers/pci/syscall.c diff --git a/.rootkeys b/.rootkeys index fbda214c94..6c0a76071c 100644 --- a/.rootkeys +++ b/.rootkeys @@ -585,10 +585,7 @@ 3ddb79bfyX7-pD6XdxY_mdNrJR20iw xen/drivers/pci/pci.c 3ddb79bf2AS7YBGwooE_Kbv7XgUqNQ xen/drivers/pci/pci.ids 3ddb79bf7sTn85WtP_8Nc2YEmmVExQ xen/drivers/pci/quirks.c -3ddb79bfkVLMq5CWjZLACPDivqxq_w xen/drivers/pci/setup-bus.c -3ddb79bfl1H1arbB0pzAEC2uPmY_3g xen/drivers/pci/setup-irq.c 3ddb79bfJaf0bkE1Y67bnll8-kjEPg xen/drivers/pci/setup-res.c -3ddb79bfIcCWJsBDNcQQE3ok2Azn-Q xen/drivers/pci/syscall.c 3eb3c87fc79FXLA6R9TvdBJNTvQDwA xen/figlet/LICENSE 3eb3c87fPL2T_zBb0bHlbZY-ACEKRw xen/figlet/Makefile 3eb3c87fmKYTC5GCh_rydFakZp9ayw xen/figlet/README diff --git a/xen/arch/x86/acpi.c b/xen/arch/x86/acpi.c index 8fda8e371b..5bbd0cd272 100644 --- a/xen/arch/x86/acpi.c +++ b/xen/arch/x86/acpi.c @@ -37,7 +37,6 @@ #include #include #include -#include #include #include #include @@ -45,14 +44,16 @@ #define PREFIX "ACPI: " -int acpi_lapic = 0; -int acpi_ioapic = 0; +int acpi_lapic; +int acpi_ioapic; +int acpi_strict; +acpi_interrupt_flags acpi_sci_flags __initdata; +int acpi_sci_override_gsi __initdata; /* -------------------------------------------------------------------------- Boot-time Configuration -------------------------------------------------------------------------- */ -#ifdef CONFIG_ACPI_BOOT int acpi_noirq __initdata = 0; /* skip ACPI IRQ initialization */ int acpi_ht __initdata = 1; /* enable HT */ @@ -210,6 +211,59 @@ acpi_parse_ioapic ( return 0; } +/* + * Parse Interrupt Source Override for the ACPI SCI + */ +static void +acpi_sci_ioapic_setup(u32 gsi, u16 polarity, u16 trigger) +{ + if (trigger == 0) /* compatible SCI trigger is level */ + trigger = 3; + + if (polarity == 0) /* compatible SCI polarity is low */ + polarity = 3; + + /* Command-line over-ride via acpi_sci= */ + if (acpi_sci_flags.trigger) + trigger = acpi_sci_flags.trigger; + + if (acpi_sci_flags.polarity) + polarity = acpi_sci_flags.polarity; + + /* + * mp_config_acpi_legacy_irqs() already setup IRQs < 16 + * If GSI is < 16, this will update its flags, + * else it will create a new mp_irqs[] entry. + */ + mp_override_legacy_irq(gsi, polarity, trigger, gsi); + + /* + * stash over-ride to indicate we've been here + * and for later update of acpi_fadt + */ + acpi_sci_override_gsi = gsi; + return; +} + +static int __init +acpi_parse_fadt(unsigned long phys, unsigned long size) +{ + struct fadt_descriptor_rev2 *fadt =0; + + fadt = (struct fadt_descriptor_rev2*) __acpi_map_table(phys,size); + if (!fadt) { + printk(KERN_WARNING PREFIX "Unable to map FADT\n"); + return 0; + } + +#ifdef CONFIG_ACPI_INTERPRETER + /* initialize sci_int early for INT_SRC_OVR MADT parsing */ + acpi_fadt.sci_int = fadt->sci_int; +#endif + + return 0; +} + static int __init acpi_parse_int_src_ovr ( @@ -223,6 +277,12 @@ acpi_parse_int_src_ovr ( acpi_table_print_madt_entry(header); + if (intsrc->bus_irq == acpi_fadt.sci_int) { + acpi_sci_ioapic_setup(intsrc->global_irq, + intsrc->flags.polarity, intsrc->flags.trigger); + return 0; + } + mp_override_legacy_irq ( intsrc->bus_irq, intsrc->flags.polarity, @@ -303,7 +363,7 @@ acpi_find_rsdp (void) * acpi_lapic = 1 if LAPIC found * acpi_ioapic = 1 if IOAPIC found * if (acpi_lapic && acpi_ioapic) smp_found_config = 1; - * if acpi_blacklisted() acpi_disabled = 1; + * if acpi_blacklisted() disable_acpi() * acpi_irq_model=... * ... * @@ -330,14 +390,14 @@ acpi_boot_init (void) */ result = acpi_table_init(); if (result) { - acpi_disabled = 1; + disable_acpi(); return result; } result = acpi_blacklisted(); if (result) { printk(KERN_NOTICE PREFIX "BIOS listed in blacklist, disabling ACPI support\n"); - acpi_disabled = 1; + disable_acpi(); return result; } @@ -440,6 +500,9 @@ acpi_boot_init (void) /* Build a default routing table for legacy (ISA) interrupts. */ mp_config_acpi_legacy_irqs(); + /* Record sci_int for use when looking for MADT sci_int override */ + acpi_table_parse(ACPI_FADT, acpi_parse_fadt); + result = acpi_table_parse_madt(ACPI_MADT_INT_SRC_OVR, acpi_parse_int_src_ovr); if (result < 0) { printk(KERN_ERR PREFIX "Error parsing interrupt source overrides entry\n"); @@ -447,6 +510,13 @@ acpi_boot_init (void) return result; } + /* + * If BIOS did not supply an INT_SRC_OVR for the SCI + * pretend we got one so we can set the SCI flags. + */ + if (!acpi_sci_override_gsi) + acpi_sci_ioapic_setup(acpi_fadt.sci_int, 0, 0); + result = acpi_table_parse_madt(ACPI_MADT_NMI_SRC, acpi_parse_nmi_src); if (result < 0) { printk(KERN_ERR PREFIX "Error parsing NMI SRC entry\n"); @@ -468,17 +538,15 @@ acpi_boot_init (void) return 0; } -#endif /*CONFIG_ACPI_BOOT*/ #ifdef CONFIG_ACPI_BUS /* - * "acpi_pic_sci=level" (current default) - * programs the PIC-mode SCI to Level Trigger. - * (NO-OP if the BIOS set Level Trigger already) + * acpi_pic_sci_set_trigger() * - * If a PIC-mode SCI is not recogznied or gives spurious IRQ7's - * it may require Edge Trigger -- use "acpi_pic_sci=edge" - * (NO-OP if the BIOS set Edge Trigger already) + * use ELCR to set PIC-mode trigger type for SCI + * + * If a PIC-mode SCI is not recognized or gives spurious IRQ7's + * it may require Edge Trigger -- use "acpi_sci=edge" * * Port 0x4d0-4d1 are ECLR1 and ECLR2, the Edge/Level Control Registers * for the 8259 PIC. bit[n] = 1 means irq[n] is Level, otherwise Edge. @@ -486,56 +554,36 @@ acpi_boot_init (void) * ECLR2 is IRQ's 8-15 (IRQ 8, 13 must be 0) */ -static __initdata int acpi_pic_sci_trigger; /* 0: level, 1: edge */ - void __init -acpi_pic_sci_set_trigger(unsigned int irq) +acpi_pic_sci_set_trigger(unsigned int irq, u16 trigger) { unsigned char mask = 1 << (irq & 7); unsigned int port = 0x4d0 + (irq >> 3); unsigned char val = inb(port); - + printk(PREFIX "IRQ%d SCI:", irq); if (!(val & mask)) { printk(" Edge"); - if (!acpi_pic_sci_trigger) { + if (trigger == 3) { printk(" set to Level"); outb(val | mask, port); } } else { printk(" Level"); - if (acpi_pic_sci_trigger) { + if (trigger == 1) { printk(" set to Edge"); - outb(val | mask, port); + outb(val & ~mask, port); } } printk(" Trigger.\n"); } -int __init -acpi_pic_sci_setup(char *str) -{ - while (str && *str) { - if (strncmp(str, "level", 5) == 0) - acpi_pic_sci_trigger = 0; /* force level trigger */ - if (strncmp(str, "edge", 4) == 0) - acpi_pic_sci_trigger = 1; /* force edge trigger */ - str = strchr(str, ','); - if (str) - str += strspn(str, ", \t"); - } - return 1; -} - -__setup("acpi_pic_sci=", acpi_pic_sci_setup); - #endif /* CONFIG_ACPI_BUS */ - /* -------------------------------------------------------------------------- Low-Level Sleep Support -------------------------------------------------------------------------- */ @@ -578,7 +626,7 @@ static void acpi_create_identity_pmd (void) pgd_t *pgd; int i; - ptep = (pte_t*)alloc_xenheap_page(); + ptep = (pte_t*)__get_free_page(GFP_KERNEL); /* fill page with low mapping */ for (i = 0; i < PTRS_PER_PTE; i++) @@ -607,7 +655,7 @@ static void acpi_restore_pmd (void) { set_pmd(pmd, saved_pmd); local_flush_tlb(); - free_xenheap_page((unsigned long)ptep); + free_page((unsigned long)ptep); } /** @@ -652,7 +700,8 @@ void acpi_restore_state_mem (void) void __init acpi_reserve_bootmem(void) { acpi_wakeup_address = (unsigned long)alloc_bootmem_low(PAGE_SIZE); - printk(KERN_DEBUG "ACPI: have wakeup address 0x%8.8lx\n", acpi_wakeup_address); + if (!acpi_wakeup_address) + printk(KERN_ERR "ACPI: Cannot allocate lowmem, S3 disabled.\n"); } void do_suspend_lowlevel_s4bios(int resume) diff --git a/xen/arch/x86/io_apic.c b/xen/arch/x86/io_apic.c index 8e172ae935..5ab74351b8 100644 --- a/xen/arch/x86/io_apic.c +++ b/xen/arch/x86/io_apic.c @@ -1797,7 +1797,11 @@ int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int a entry.trigger = edge_level; entry.polarity = active_high_low; - add_pin_to_irq(irq, ioapic, pin); + /* + * IRQs < 16 are already in the irq_2_pin[] map + */ + if (irq >= 16) + add_pin_to_irq(irq, ioapic, pin); entry.vector = assign_irq_vector(irq); diff --git a/xen/arch/x86/pci-irq.c b/xen/arch/x86/pci-irq.c index cf19e9e9a1..e0f157846e 100644 --- a/xen/arch/x86/pci-irq.c +++ b/xen/arch/x86/pci-irq.c @@ -592,6 +592,7 @@ static __init int intel_router_probe(struct irq_router *r, struct pci_dev *route case PCI_DEVICE_ID_INTEL_82801E_0: case PCI_DEVICE_ID_INTEL_82801EB_0: case PCI_DEVICE_ID_INTEL_ESB_0: + case PCI_DEVICE_ID_INTEL_ICH6_0: r->name = "PIIX/ICH"; r->get = pirq_piix_get; r->set = pirq_piix_set; diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c index 831a27e092..e629930ab6 100644 --- a/xen/arch/x86/setup.c +++ b/xen/arch/x86/setup.c @@ -46,11 +46,6 @@ int acpi_disabled = 1; #endif EXPORT_SYMBOL(acpi_disabled); -#ifdef CONFIG_ACPI_BOOT -extern int __initdata acpi_ht; -int acpi_force __initdata = 0; -#endif - int phys_proc_id[NR_CPUS]; int logical_proc_id[NR_CPUS]; diff --git a/xen/drivers/pci/setup-bus.c b/xen/drivers/pci/setup-bus.c deleted file mode 100644 index 0819c99b59..0000000000 --- a/xen/drivers/pci/setup-bus.c +++ /dev/null @@ -1,400 +0,0 @@ -/* - * drivers/pci/setup-bus.c - * - * Extruded from code written by - * Dave Rusling (david.rusling@reo.mts.dec.com) - * David Mosberger (davidm@cs.arizona.edu) - * David Miller (davem@redhat.com) - * - * Support routines for initializing a PCI subsystem. - */ - -/* - * Nov 2000, Ivan Kokshaysky - * PCI-PCI bridges cleanup, sorted resource allocation. - * Feb 2002, Ivan Kokshaysky - * Converted to allocation in 3 passes, which gives - * tighter packing. Prefetchable range support. - */ - -#include -#include -#include -#include -#include -#include -#include - - -#define DEBUG_CONFIG 1 -#if DEBUG_CONFIG -# define DBGC(args) printk args -#else -# define DBGC(args) -#endif - -#define ROUND_UP(x, a) (((x) + (a) - 1) & ~((a) - 1)) - -static int __init -pbus_assign_resources_sorted(struct pci_bus *bus) -{ - struct list_head *ln; - struct resource *res; - struct resource_list head, *list, *tmp; - int idx, found_vga = 0; - - head.next = NULL; - for (ln=bus->devices.next; ln != &bus->devices; ln=ln->next) { - struct pci_dev *dev = pci_dev_b(ln); - u16 class = dev->class >> 8; - u16 cmd; - - /* First, disable the device to avoid side - effects of possibly overlapping I/O and - memory ranges. - Leave VGA enabled - for obvious reason. :-) - Same with all sorts of bridges - they may - have VGA behind them. */ - if (class == PCI_CLASS_DISPLAY_VGA - || class == PCI_CLASS_NOT_DEFINED_VGA) - found_vga = 1; - else if (class >> 8 != PCI_BASE_CLASS_BRIDGE) { - pci_read_config_word(dev, PCI_COMMAND, &cmd); - cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY - | PCI_COMMAND_MASTER); - pci_write_config_word(dev, PCI_COMMAND, cmd); - } - - pdev_sort_resources(dev, &head); - } - - for (list = head.next; list;) { - res = list->res; - idx = res - &list->dev->resource[0]; - pci_assign_resource(list->dev, idx); - tmp = list; - list = list->next; - xfree(tmp); - } - - return found_vga; -} - -/* Initialize bridges with base/limit values we have collected. - PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998) - requires that if there is no I/O ports or memory behind the - bridge, corresponding range must be turned off by writing base - value greater than limit to the bridge's base/limit registers. */ -static void __init -pci_setup_bridge(struct pci_bus *bus) -{ - struct pbus_set_ranges_data ranges; - struct pci_dev *bridge = bus->self; - u32 l; - - if (!bridge || (bridge->class >> 8) != PCI_CLASS_BRIDGE_PCI) - return; - - ranges.io_start = bus->resource[0]->start; - ranges.io_end = bus->resource[0]->end; - ranges.mem_start = bus->resource[1]->start; - ranges.mem_end = bus->resource[1]->end; - ranges.prefetch_start = bus->resource[2]->start; - ranges.prefetch_end = bus->resource[2]->end; - pcibios_fixup_pbus_ranges(bus, &ranges); - - DBGC((KERN_INFO "PCI: Bus %d, bridge: %s\n", - bus->number, bridge->name)); - - /* Set up the top and bottom of the PCI I/O segment for this bus. */ - if (bus->resource[0]->flags & IORESOURCE_IO) { - pci_read_config_dword(bridge, PCI_IO_BASE, &l); - l &= 0xffff0000; - l |= (ranges.io_start >> 8) & 0x00f0; - l |= ranges.io_end & 0xf000; - /* Set up upper 16 bits of I/O base/limit. */ - pci_write_config_word(bridge, PCI_IO_BASE_UPPER16, - ranges.io_start >> 16); - pci_write_config_word(bridge, PCI_IO_LIMIT_UPPER16, - ranges.io_end >> 16); - DBGC((KERN_INFO " IO window: %04lx-%04lx\n", - ranges.io_start, ranges.io_end)); - } - else { - /* Clear upper 16 bits of I/O base/limit. */ - pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0); - l = 0x00f0; - DBGC((KERN_INFO " IO window: disabled.\n")); - } - pci_write_config_dword(bridge, PCI_IO_BASE, l); - - /* Set up the top and bottom of the PCI Memory segment - for this bus. */ - if (bus->resource[1]->flags & IORESOURCE_MEM) { - l = (ranges.mem_start >> 16) & 0xfff0; - l |= ranges.mem_end & 0xfff00000; - DBGC((KERN_INFO " MEM window: %08lx-%08lx\n", - ranges.mem_start, ranges.mem_end)); - } - else { - l = 0x0000fff0; - DBGC((KERN_INFO " MEM window: disabled.\n")); - } - pci_write_config_dword(bridge, PCI_MEMORY_BASE, l); - - /* Clear out the upper 32 bits of PREF base/limit. */ - pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, 0); - pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0); - - /* Set up PREF base/limit. */ - if (bus->resource[2]->flags & IORESOURCE_PREFETCH) { - l = (ranges.prefetch_start >> 16) & 0xfff0; - l |= ranges.prefetch_end & 0xfff00000; - DBGC((KERN_INFO " PREFETCH window: %08lx-%08lx\n", - ranges.prefetch_start, ranges.prefetch_end)); - } - else { - l = 0x0000fff0; - DBGC((KERN_INFO " PREFETCH window: disabled.\n")); - } - pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l); - - /* Check if we have VGA behind the bridge. - Enable ISA in either case (FIXME!). */ - l = (bus->resource[0]->flags & IORESOURCE_BUS_HAS_VGA) ? 0x0c : 0x04; - pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, l); -} - -/* Check whether the bridge supports optional I/O and - prefetchable memory ranges. If not, the respective - base/limit registers must be read-only and read as 0. */ -static void __init -pci_bridge_check_ranges(struct pci_bus *bus) -{ - u16 io; - u32 pmem; - struct pci_dev *bridge = bus->self; - struct resource *b_res; - - if (!bridge || (bridge->class >> 8) != PCI_CLASS_BRIDGE_PCI) - return; - - b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; - b_res[1].flags |= IORESOURCE_MEM; - - pci_read_config_word(bridge, PCI_IO_BASE, &io); - if (!io) { - pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0); - pci_read_config_word(bridge, PCI_IO_BASE, &io); - pci_write_config_word(bridge, PCI_IO_BASE, 0x0); - } - if (io) - b_res[0].flags |= IORESOURCE_IO; - /* DECchip 21050 pass 2 errata: the bridge may miss an address - disconnect boundary by one PCI data phase. - Workaround: do not use prefetching on this device. */ - if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001) - return; - pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); - if (!pmem) { - pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, - 0xfff0fff0); - pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); - pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0); - } - if (pmem) - b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH; -} - -/* Sizing the IO windows of the PCI-PCI bridge is trivial, - since these windows have 4K granularity and the IO ranges - of non-bridge PCI devices are limited to 256 bytes. - We must be careful with the ISA aliasing though. */ -static void __init -pbus_size_io(struct pci_bus *bus) -{ - struct list_head *ln; - struct resource *b_res = bus->resource[0]; - unsigned long size = 0, size1 = 0; - - if (!(b_res->flags & IORESOURCE_IO)) - return; - - for (ln=bus->devices.next; ln != &bus->devices; ln=ln->next) { - struct pci_dev *dev = pci_dev_b(ln); - int i; - - for (i = 0; i < PCI_NUM_RESOURCES; i++) { - struct resource *r = &dev->resource[i]; - unsigned long r_size; - - if (r->parent || !(r->flags & IORESOURCE_IO)) - continue; - r_size = r->end - r->start + 1; - - if (r_size < 0x400) - /* Might be re-aligned for ISA */ - size += r_size; - else - size1 += r_size; - } - /* ??? Reserve some resources for CardBus. */ - if ((dev->class >> 8) == PCI_CLASS_BRIDGE_CARDBUS) - size1 += 4*1024; - } -/* To be fixed in 2.5: we should have sort of HAVE_ISA - flag in the struct pci_bus. */ -#if defined(CONFIG_ISA) || defined(CONFIG_EISA) - size = (size & 0xff) + ((size & ~0xffUL) << 2); -#endif - size = ROUND_UP(size + size1, 4096); - if (!size) { - b_res->flags = 0; - return; - } - /* Alignment of the IO window is always 4K */ - b_res->start = 4096; - b_res->end = b_res->start + size - 1; -} - -/* Calculate the size of the bus and minimal alignment which - guarantees that all child resources fit in this size. */ -static void __init -pbus_size_mem(struct pci_bus *bus, unsigned long mask, unsigned long type) -{ - struct list_head *ln; - unsigned long min_align, align, size; - unsigned long aligns[12]; /* Alignments from 1Mb to 2Gb */ - int order, max_order; - struct resource *b_res = (type & IORESOURCE_PREFETCH) ? - bus->resource[2] : bus->resource[1]; - - memset(aligns, 0, sizeof(aligns)); - max_order = 0; - size = 0; - - for (ln=bus->devices.next; ln != &bus->devices; ln=ln->next) { - struct pci_dev *dev = pci_dev_b(ln); - int i; - - for (i = 0; i < PCI_NUM_RESOURCES; i++) { - struct resource *r = &dev->resource[i]; - unsigned long r_size; - - if (r->parent || (r->flags & mask) != type) - continue; - r_size = r->end - r->start + 1; - /* For bridges size != alignment */ - align = (i < PCI_BRIDGE_RESOURCES) ? r_size : r->start; - order = ffz(~align) - 20; - if (order > 11) { - printk(KERN_WARNING "PCI: region %s/%d " - "too large: %lx-%lx\n", - dev->slot_name, i, r->start, r->end); - r->flags = 0; - continue; - } - size += r_size; - if (order < 0) - order = 0; - /* Exclude ranges with size > align from - calculation of the alignment. */ - if (r_size == align) - aligns[order] += align; - if (order > max_order) - max_order = order; - } - /* ??? Reserve some resources for CardBus. */ - if ((dev->class >> 8) == PCI_CLASS_BRIDGE_CARDBUS) { - size += 1UL << 24; /* 16 Mb */ - aligns[24 - 20] += 1UL << 24; - } - } - - align = 0; - min_align = 0; - for (order = 0; order <= max_order; order++) { - unsigned long align1 = 1UL << (order + 20); - - if (!align) - min_align = align1; - else if (ROUND_UP(align + min_align, min_align) < align1) - min_align = align1 >> 1; - align += aligns[order]; - } - size = ROUND_UP(size, min_align); - if (!size) { - b_res->flags = 0; - return; - } - b_res->start = min_align; - b_res->end = size + min_align - 1; -} - -void __init -pbus_size_bridges(struct pci_bus *bus) -{ - struct list_head *ln; - unsigned long mask, type; - - for (ln=bus->children.next; ln != &bus->children; ln=ln->next) - pbus_size_bridges(pci_bus_b(ln)); - - /* The root bus? */ - if (!bus->self) - return; - - pci_bridge_check_ranges(bus); - - pbus_size_io(bus); - - mask = type = IORESOURCE_MEM; - /* If the bridge supports prefetchable range, size it separately. */ - if (bus->resource[2] && - bus->resource[2]->flags & IORESOURCE_PREFETCH) { - pbus_size_mem(bus, IORESOURCE_PREFETCH, IORESOURCE_PREFETCH); - mask |= IORESOURCE_PREFETCH; /* Size non-prefetch only. */ - } - pbus_size_mem(bus, mask, type); -} - -void __init -pbus_assign_resources(struct pci_bus *bus) -{ - struct list_head *ln; - int found_vga = pbus_assign_resources_sorted(bus); - - if (found_vga) { - struct pci_bus *b; - - /* Propagate presence of the VGA to upstream bridges */ - for (b = bus; b->parent; b = b->parent) { - b->resource[0]->flags |= IORESOURCE_BUS_HAS_VGA; - } - } - for (ln=bus->children.next; ln != &bus->children; ln=ln->next) { - struct pci_bus *b = pci_bus_b(ln); - - pbus_assign_resources(b); - pci_setup_bridge(b); - } -} - -void __init -pci_assign_unassigned_resources(void) -{ - struct list_head *ln; - struct pci_dev *dev; - - /* Depth first, calculate sizes and alignments of all - subordinate buses. */ - for(ln=pci_root_buses.next; ln != &pci_root_buses; ln=ln->next) - pbus_size_bridges(pci_bus_b(ln)); - /* Depth last, allocate resources and update the hardware. */ - for(ln=pci_root_buses.next; ln != &pci_root_buses; ln=ln->next) - pbus_assign_resources(pci_bus_b(ln)); - - pci_for_each_dev(dev) { - pdev_enable_device(dev); - } -} diff --git a/xen/drivers/pci/setup-irq.c b/xen/drivers/pci/setup-irq.c deleted file mode 100644 index 919913b94d..0000000000 --- a/xen/drivers/pci/setup-irq.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * drivers/pci/setup-irq.c - * - * Extruded from code written by - * Dave Rusling (david.rusling@reo.mts.dec.com) - * David Mosberger (davidm@cs.arizona.edu) - * David Miller (davem@redhat.com) - * - * Support routines for initializing a PCI subsystem. - */ - - -#include -#include -#include -#include -#include -#include - - -#define DEBUG_CONFIG 0 -#if DEBUG_CONFIG -# define DBGC(args) printk args -#else -# define DBGC(args) -#endif - - -static void __init -pdev_fixup_irq(struct pci_dev *dev, - u8 (*swizzle)(struct pci_dev *, u8 *), - int (*map_irq)(struct pci_dev *, u8, u8)) -{ - u8 pin, slot; - int irq; - - /* If this device is not on the primary bus, we need to figure out - which interrupt pin it will come in on. We know which slot it - will come in on 'cos that slot is where the bridge is. Each - time the interrupt line passes through a PCI-PCI bridge we must - apply the swizzle function. */ - - pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); - /* Cope with 0 and illegal. */ - if (pin == 0 || pin > 4) - pin = 1; - - /* Follow the chain of bridges, swizzling as we go. */ - slot = (*swizzle)(dev, &pin); - - irq = (*map_irq)(dev, slot, pin); - if (irq == -1) - irq = 0; - dev->irq = irq; - - DBGC((KERN_ERR "PCI fixup irq: (%s) got %d\n", dev->name, dev->irq)); - - /* Always tell the device, so the driver knows what is - the real IRQ to use; the device does not use it. */ - pcibios_update_irq(dev, irq); -} - -void __init -pci_fixup_irqs(u8 (*swizzle)(struct pci_dev *, u8 *), - int (*map_irq)(struct pci_dev *, u8, u8)) -{ - struct pci_dev *dev; - pci_for_each_dev(dev) { - pdev_fixup_irq(dev, swizzle, map_irq); - } -} diff --git a/xen/drivers/pci/syscall.c b/xen/drivers/pci/syscall.c deleted file mode 100644 index d55c52e835..0000000000 --- a/xen/drivers/pci/syscall.c +++ /dev/null @@ -1,144 +0,0 @@ -/* - * pci_syscall.c - * - * For architectures where we want to allow direct access - * to the PCI config stuff - it would probably be preferable - * on PCs too, but there people just do it by hand with the - * magic northbridge registers.. - */ - -#include -#include -#include -#include -#include - - -asmlinkage long -sys_pciconfig_read(unsigned long bus, unsigned long dfn, - unsigned long off, unsigned long len, void *buf) -{ - struct pci_dev *dev; - u8 byte; - u16 word; - u32 dword; - long err, cfg_ret; - - err = -EPERM; - if (!capable(CAP_SYS_ADMIN)) - goto error; - - err = -ENODEV; - dev = pci_find_slot(bus, dfn); - if (!dev) - goto error; - - lock_kernel(); - switch (len) { - case 1: - cfg_ret = pci_read_config_byte(dev, off, &byte); - break; - case 2: - cfg_ret = pci_read_config_word(dev, off, &word); - break; - case 4: - cfg_ret = pci_read_config_dword(dev, off, &dword); - break; - default: - err = -EINVAL; - unlock_kernel(); - goto error; - }; - unlock_kernel(); - - err = -EIO; - if (cfg_ret != PCIBIOS_SUCCESSFUL) - goto error; - - switch (len) { - case 1: - err = put_user(byte, (unsigned char *)buf); - break; - case 2: - err = put_user(word, (unsigned short *)buf); - break; - case 4: - err = put_user(dword, (unsigned int *)buf); - break; - }; - return err; - -error: - /* ??? XFree86 doesn't even check the return value. They - just look for 0xffffffff in the output, since that's what - they get instead of a machine check on x86. */ - switch (len) { - case 1: - put_user(-1, (unsigned char *)buf); - break; - case 2: - put_user(-1, (unsigned short *)buf); - break; - case 4: - put_user(-1, (unsigned int *)buf); - break; - }; - return err; -} - -asmlinkage long -sys_pciconfig_write(unsigned long bus, unsigned long dfn, - unsigned long off, unsigned long len, void *buf) -{ - struct pci_dev *dev; - u8 byte; - u16 word; - u32 dword; - int err = 0; - - if (!capable(CAP_SYS_ADMIN)) - return -EPERM; - if (!pcibios_present()) - return -ENOSYS; - - dev = pci_find_slot(bus, dfn); - if (!dev) - return -ENODEV; - - lock_kernel(); - switch(len) { - case 1: - err = get_user(byte, (u8 *)buf); - if (err) - break; - err = pci_write_config_byte(dev, off, byte); - if (err != PCIBIOS_SUCCESSFUL) - err = -EIO; - break; - - case 2: - err = get_user(word, (u16 *)buf); - if (err) - break; - err = pci_write_config_word(dev, off, word); - if (err != PCIBIOS_SUCCESSFUL) - err = -EIO; - break; - - case 4: - err = get_user(dword, (u32 *)buf); - if (err) - break; - err = pci_write_config_dword(dev, off, dword); - if (err != PCIBIOS_SUCCESSFUL) - err = -EIO; - break; - - default: - err = -EINVAL; - break; - }; - unlock_kernel(); - - return err; -} diff --git a/xen/include/asm-x86/acpi.h b/xen/include/asm-x86/acpi.h index be7d6dfda7..3a15181819 100644 --- a/xen/include/asm-x86/acpi.h +++ b/xen/include/asm-x86/acpi.h @@ -26,6 +26,9 @@ #ifndef _ASM_ACPI_H #define _ASM_ACPI_H +#include +#include + #define COMPILER_DEPENDENT_INT64 long long #define COMPILER_DEPENDENT_UINT64 unsigned long long @@ -50,42 +53,36 @@ #define ACPI_ENABLE_IRQS() __sti() #define ACPI_FLUSH_CPU_CACHE() wbinvd() -/* - * A brief explanation as GNU inline assembly is a bit hairy - * %0 is the output parameter in EAX ("=a") - * %1 and %2 are the input parameters in ECX ("c") - * and an immediate value ("i") respectively - * All actual register references are preceded with "%%" as in "%%edx" - * Immediate values in the assembly are preceded by "$" as in "$0x1" - * The final asm parameter are the operation altered non-output registers. - */ + +static inline int +__acpi_acquire_global_lock (unsigned int *lock) +{ + unsigned int old, new, val; + do { + old = *lock; + new = (((old & ~0x3) + 2) + ((old >> 1) & 0x1)); + val = cmpxchg(lock, old, new); + } while (unlikely (val != old)); + return (new < 3) ? -1 : 0; +} + +static inline int +__acpi_release_global_lock (unsigned int *lock) +{ + unsigned int old, new, val; + do { + old = *lock; + new = old & ~0x3; + val = cmpxchg(lock, old, new); + } while (unlikely (val != old)); + return old & 0x1; +} + #define ACPI_ACQUIRE_GLOBAL_LOCK(GLptr, Acq) \ - do { \ - int dummy; \ - asm("1: movl (%1),%%eax;" \ - "movl %%eax,%%edx;" \ - "andl %2,%%edx;" \ - "btsl $0x1,%%edx;" \ - "adcl $0x0,%%edx;" \ - "lock; cmpxchgl %%edx,(%1);" \ - "jnz 1b;" \ - "cmpb $0x3,%%dl;" \ - "sbbl %%eax,%%eax" \ - :"=a"(Acq),"=c"(dummy):"c"(GLptr),"i"(~1L):"dx"); \ - } while(0) + ((Acq) = __acpi_acquire_global_lock((unsigned int *) GLptr)) #define ACPI_RELEASE_GLOBAL_LOCK(GLptr, Acq) \ - do { \ - int dummy; \ - asm("1: movl (%1),%%eax;" \ - "movl %%eax,%%edx;" \ - "andl %2,%%edx;" \ - "lock; cmpxchgl %%edx,(%1);" \ - "jnz 1b;" \ - "andl $0x1,%%eax" \ - :"=a"(Acq),"=c"(dummy):"c"(GLptr),"i"(~3L):"dx"); \ - } while(0) - + ((Acq) = __acpi_release_global_lock((unsigned int *) GLptr)) /* * Math helper asm macros @@ -108,7 +105,10 @@ extern int acpi_lapic; extern int acpi_ioapic; extern int acpi_noirq; +extern int acpi_strict; extern int acpi_disabled; +extern int acpi_ht; +static inline void disable_acpi(void) { acpi_disabled = 1; acpi_ht = 0; } /* Fixmap pages to reserve for ACPI boot-time tables (see fixmap.h) */ #define FIX_ACPI_PAGES 4 diff --git a/xen/include/xen/pci_ids.h b/xen/include/xen/pci_ids.h index ee352a9cb5..f91e7d9677 100644 --- a/xen/include/xen/pci_ids.h +++ b/xen/include/xen/pci_ids.h @@ -287,6 +287,8 @@ #define PCI_DEVICE_ID_ATI_RADEON_Ig 0x4967 /* Radeon RV280 (9200) */ #define PCI_DEVICE_ID_ATI_RADEON_Y_ 0x5960 +#define PCI_DEVICE_ID_ATI_RADEON_Ya 0x5961 +#define PCI_DEVICE_ID_ATI_RADEON_Yd 0x5964 /* Radeon R300 (9700) */ #define PCI_DEVICE_ID_ATI_RADEON_ND 0x4e44 #define PCI_DEVICE_ID_ATI_RADEON_NE 0x4e45 @@ -315,6 +317,8 @@ #define PCI_DEVICE_ID_ATI_RADEON_Lg 0x4c67 /* RadeonIGP */ #define PCI_DEVICE_ID_ATI_RADEON_IGP 0xCAB0 +/* ATI IXP Chipset */ +#define PCI_DEVICE_ID_ATI_IXP_IDE 0x4349 #define PCI_VENDOR_ID_VLSI 0x1004 #define PCI_DEVICE_ID_VLSI_82C592 0x0005 @@ -425,6 +429,7 @@ #define PCI_DEVICE_ID_AMD_LANCE 0x2000 #define PCI_DEVICE_ID_AMD_LANCE_HOME 0x2001 #define PCI_DEVICE_ID_AMD_SCSI 0x2020 +#define PCI_DEVICE_ID_AMD_SERENADE 0x36c0 #define PCI_DEVICE_ID_AMD_FE_GATE_7006 0x7006 #define PCI_DEVICE_ID_AMD_FE_GATE_7007 0x7007 #define PCI_DEVICE_ID_AMD_FE_GATE_700C 0x700C @@ -523,6 +528,7 @@ #define PCI_DEVICE_ID_SI_6202 0x0002 #define PCI_DEVICE_ID_SI_503 0x0008 #define PCI_DEVICE_ID_SI_ACPI 0x0009 +#define PCI_DEVICE_ID_SI_180 0x0180 #define PCI_DEVICE_ID_SI_5597_VGA 0x0200 #define PCI_DEVICE_ID_SI_6205 0x0205 #define PCI_DEVICE_ID_SI_501 0x0406 @@ -657,6 +663,8 @@ #define PCI_DEVICE_ID_TI_4410 0xac41 #define PCI_DEVICE_ID_TI_4451 0xac42 #define PCI_DEVICE_ID_TI_1420 0xac51 +#define PCI_DEVICE_ID_TI_1520 0xac55 +#define PCI_DEVICE_ID_TI_1510 0xac56 #define PCI_VENDOR_ID_SONY 0x104d #define PCI_DEVICE_ID_SONY_CXD3222 0x8039 @@ -750,6 +758,7 @@ #define PCI_DEVICE_ID_APPLE_UNI_N_AGP_P 0x0027 #define PCI_DEVICE_ID_APPLE_UNI_N_AGP15 0x002d #define PCI_DEVICE_ID_APPLE_UNI_N_FW2 0x0030 +#define PCI_DEVICE_ID_APPLE_TIGON3 0x1645 #define PCI_VENDOR_ID_YAMAHA 0x1073 #define PCI_DEVICE_ID_YAMAHA_724 0x0004 @@ -969,9 +978,15 @@ #define PCI_DEVICE_ID_NVIDIA_VTNT2 0x002C #define PCI_DEVICE_ID_NVIDIA_UVTNT2 0x002D #define PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE 0x0065 +#define PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE 0x0085 +#define PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA 0x008e #define PCI_DEVICE_ID_NVIDIA_ITNT2 0x00A0 #define PCI_DEVICE_ID_NVIDIA_NFORCE3 0x00d1 +#define PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE 0x00d5 #define PCI_DEVICE_ID_NVIDIA_NFORCE3S 0x00e1 +#define PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA 0x00e3 +#define PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE 0x00e5 +#define PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2 0x00ee #define PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR 0x0100 #define PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR 0x0101 #define PCI_DEVICE_ID_NVIDIA_QUADRO 0x0103 @@ -1677,6 +1692,12 @@ #define PCI_DEVICE_ID_TIGON3_5901_2 0x170e #define PCI_DEVICE_ID_BCM4401 0x4401 +#define PCI_VENDOR_ID_ENE 0x1524 +#define PCI_DEVICE_ID_ENE_1211 0x1211 +#define PCI_DEVICE_ID_ENE_1225 0x1225 +#define PCI_DEVICE_ID_ENE_1410 0x1410 +#define PCI_DEVICE_ID_ENE_1420 0x1420 + #define PCI_VENDOR_ID_SYBA 0x1592 #define PCI_DEVICE_ID_SYBA_2P_EPP 0x0782 #define PCI_DEVICE_ID_SYBA_1P_ECP 0x0783 @@ -1853,7 +1874,7 @@ #define PCI_DEVICE_ID_INTEL_82801DB_7 0x24c7 #define PCI_DEVICE_ID_INTEL_82801DB_10 0x24ca #define PCI_DEVICE_ID_INTEL_82801DB_11 0x24cb -#define PCI_DEVICE_ID_INTEL_82801DB_12 0x24cc +#define PCI_DEVICE_ID_INTEL_82801DB_12 0x24cc #define PCI_DEVICE_ID_INTEL_82801DB_13 0x24cd #define PCI_DEVICE_ID_INTEL_82801EB_0 0x24d0 #define PCI_DEVICE_ID_INTEL_82801EB_1 0x24d1 @@ -1880,6 +1901,10 @@ #define PCI_DEVICE_ID_INTEL_ESB_11 0x25ac #define PCI_DEVICE_ID_INTEL_ESB_12 0x25ad #define PCI_DEVICE_ID_INTEL_ESB_13 0x25ae +#define PCI_DEVICE_ID_INTEL_ICH6_0 0x2640 +#define PCI_DEVICE_ID_INTEL_ICH6_1 0x2641 +#define PCI_DEVICE_ID_INTEL_ICH6_2 0x266f +#define PCI_DEVICE_ID_INTEL_ICH6_3 0x266e #define PCI_DEVICE_ID_INTEL_82850_HB 0x2530 #define PCI_DEVICE_ID_INTEL_82845G_HB 0x2560 #define PCI_DEVICE_ID_INTEL_80310 0x530d -- 2.30.2